Field-effect transistors (FETs) and other related insulated-gate electronic devices are mainstay components of MOS integrated circuits. A MOSFET generally consists of two closely spaced, doped regions in a substrate--the source and the drain. The region between the two is the channel above which a thin insulation layer is formed. A gate electrode is formed directly over and completely covering the insulation layer directly above the channel and a voltage applied to the gate affects the electronic properties of the channel region, whereby the MOSFET is turned on and off.
The abbreviation MOS (metal oxide semiconductor) has become somewhat of a misnomer because for many applications the gate is formed of a polysilicon material which is doped to render it conductive. Although such a gate is adequate to create a field in the channel region so as to control the state of the MOSFET, it is not without its operational problems. One of these problems is that polysilicon has a relatively high sheet resistance and therefore is not as good a conductor as metal. This, of course, results in slower devices. Hence, manufacturers of integrated circuits have taken to forming composite metal silicide electrodes and interconnections between circuit components.
As semiconductor device structures have continued to shrink below 0.25 micron, the resistivity of titanium silicide, which is commonly used as contacts for the source/drain regions and the poly gate, has become undesirably high. The reason for the increase in resistivity has to do with the standard two step process by which titanium silicide is formed. After a titanium layer has been formed via a blanket deposit, a low temperature anneal takes place to transform the titanium into the C49 phase of titanium silicide in the selective regions where a titanium and silicon interface exists. The C49 phase is a high resistivity phase and consequently undesirable as a final silicide material. The low temperature anneal prevents the reaction of titanium with the oxide regions (such as the sidewall spacers and isolation regions). After the C49 phase has been formed, the unreacted titanium portions (over the oxide regions) are removed and a second, high temperature anneal is conducted in which the C49 phase is converted into the low resistivity C54 titanium silicide phase. Unfortunately, as transistor line widths continue to decrease to 0.25 micron or less, the grain sizes of the silicide formed in the C49 phase become too large (approaching the device line width) which limit their conversion to the C54 (low resistivity) phase. Consequently, as transistor sizes decrease to 0.25 microns or less, the silicide resistivity increases in an undesirable manner due to inability to form the C54 phase.
Another problem experienced with titanium silicide contacts involve their formation using laser annealing. Laser annealing is a process by which a laser beam is radiated onto a wafer in a pulsed mode to anneal various semiconductor regions. In one type of prior art silicide formation 10, as illustrated in prior art FIG. 1, a source region 14, a drain region 16 and a poly gate 18 had silicides formed thereon with the same processing step. Unfortunately, the laser energy required to melt the source/drain regions 14 and 16 is higher than the poly gate 18; therefore the laser energy required to form the source region 14 and drain region 16 causes excessive melting of the poly gate 18 which results in degraded gate oxide quality and, in some cases, poly gate destruction.
One prior art solution to the above problems involved the addition of an amorphizing implant such as silicon or germanium to reduce the melting temperature of the poly gate 18 and source/drains 14 and 16. The goal of this process was to stay below the melting temperature of the polycrystalline, but above the melting temperature of the amorphized region which allowed for melting of the poly gate 18 and the source/drain regions 14 and 16 without melting through the entire thickness of the poly gate 18. Unfortunately, this prior art process solution adds process steps and causes increased defects, thereby resulting in increased leakage and enhanced diffusion.
Accordingly, there is a need in the art for low resistivity titanium silicide gates at device geometries less than 0.25 micron.